1. Field of the Invention
This application relates to an electrically alterable and non-volatile semiconductor memory device or an electrically writable and erasable non-volatile semiconductor memory device.
2. Description of Related Art
Document 1: "SINGLE TRANSISTOR ELECTRICALLY PROGRAMMABLE MEMORY DEVICE AND METHOD", U.S. Pat. No. 4,698,787 (Oct. 6, 1987).
Document 2: "FLASH EEPROM ARRAY WITH NEGATIVE GATE VOLTAGE ERASE OPERATION", U.S. Pat. No. 5,077,691 (Dec. 31, 1991).
Document 3: "PRESENT STATE AND FUTURE VIEW OF FLASH MEMORY", ICD91-134, 1991.
As non-volatile semiconductor memory devices, there are an ultraviolet erasable EPROM (Erasable and Programmable Read Only Memory) and an electrically writable and erasable (hereinafter referred to as "electrically alterable") EEPROM (Electrically Erasable and Programmable Read Only Memory). Further, recently an electrically erasable flash EEPROM is developed. Data stored in memory cells of the EPROM can be erased only by ultraviolet rays and cannot be erased electrically. Accordingly, the EPROM requires a package with a transparent window. Further, it is inconvenient to alter the stored data in the EPROM after mounting the EPROM on a board of a system since the EPROM must be removed from the board once. The EEPROM can be electrically altered in a system, but the EEPROM has memory cells which require a transistor or a channel area for selective isolation and accordingly the area of each memory cell is about two times larger than that of the EPROM. In order to solve the problem, a flash type EEPROM capable of electrically erasing and having a memory cell area which is the same as that of the EPROM has been developed.
The flash type EEPROM developed in the early stage is described in Document 1, for example. According to Document 1, there is provided a method and a device structure for performing electrical writing and erasing by means of a single memory transistor having a floating gate. In the erasing operation, a high voltage of 10 to 20 volts (V) is applied to a source terminal of a memory cell and a ground potential is applied to a control gate terminal to thereby generate a high electric field in a thin insulating layer between the floating gate and the source so that electrons are ejected from the floating gate by the Fowler-Nordheim tunneling (hereinafter referred to as "FN injection") to thereby lower a threshold voltage of the memory cell as viewed from the control gate. In the writing operation, by applying a voltage of 5 to 10 V to a drain terminal of the memory cell, applying a high voltage of 10 to 15 V to the control gate and connecting a source to the ground, a strong inversion area is formed in a surface of a substrate between the drain and the source to generate hot electrons (hereinafter referred to as "HE injection"), so that electrons are injected to the floating gate to thereby raise the threshold voltage of the memory cell.
Further, in pages 4 and 5 of Documents 2 and 3, another erasing method is disclosed in which a negative voltage (for example, -7 to -15 V) is applied to the control gate of the memory cell and a power supply voltage (for example, 5 V) or a ground potential is applied to the source terminal, so that electrons are ejected from the floating gate by the FN injection. In this method, as disclosed in Document 1, since a high voltage (for example, 10 to 20 V) is not required for the source terminal, the voltage in the altering operation can be advantageously lowered. Further, in this method, since the control gate of the memory cell is generally connected to a row decoder as a word line, a voltage of, for example, 0 to 5 V can be applied to control gates of non-selected memory cells to prevent the FN injection, so that erasing in a block of the word line (or a block of sector) can be attained.
In the above erasing methods, there is the problem that data stored in those memory cells which are not required to be altered are also altered, even when data of one bit stored in one memory cell is to be altered, because the erasing operation can be performed only in a group of the memory cells or a block of sector.